Double recessed transistor

ABSTRACT

A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of Ga x In 1-x As is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of Ga x In 1−x As is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of Al y In 1−y As is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

BACKGROUND OF THE INVENTION

[0001] This invention relates generally to high electron mobilitytransistors (HEMTs) and more particularly to transistors of such typewhich are fabricated with a double recess.

[0002] As is known in the art, there are several types of active devicesused at microwave and millimeter frequencies to provide amplification ofradio frequency signals. In general, one of the more commonsemiconductor devices used at these frequencies is the high electronmobility transistor (HEMT). Typically, HEMTs are formed from Group III-Vmaterials such as gallium arsenide (GaAs) or indium phosphide (InP). Ina HEMT there is a doped donor/undoped spacer layer of one material andan undoped channel layer of a different material. A heterojunction isformed between the doped donor/undoped spacer layer and the undopedchannel layer. Due to the conduction band discontinuity at theheterojunction, electrons are injected from the doped donor/undopedspacer layer into the undoped channel layer. Thus, electrons from thelarge bandgap donor layer are transferred into the narrow bandgapchannel layer where they are confined to move only in a plane parallelto the heterojunction. Consequently, there is spacial separation betweenthe donor atoms in the donor layer and the electrons in the channellayer resulting in low impurity scattering and good electron mobility.

[0003] One device which has been found to provide good devicecharacteristics such as breakdown voltage, output currents, andpinch-off voltage is a double recessed HEMT. Such a device is fabricatedwith two aligned recesses in which the gate is formed. The recesses aretypically formed by wet etching the device. The etching process isperiodically interrupted and the device is tested for certaincharacteristics, e.g., current. If the characteristics meet the desiredcriteria, then etching for that recess is terminated. Otherwise, theetching continues. This process continues until both recesses meet theestablished criteria. This process takes time and money to repeatedlystop the etching and test the device. Also, the etching is not uniformacross the wafer, resulting in inconsistent device characteristicsacross the wafer and low yield of acceptable devices on the wafer.

SUMMARY OF THE INVENTION

[0004] In accordance with the present invention, a transistor structureis provided. This structure has a source electrode and a drainelectrode. A doped cap layer of Ga_(x)In_(1-x)As is disposed below andin ohmic contact with the source electrode and the drain electrode andprovides a cap layer opening. An undoped resistive layer ofGa_(x)In_(1-x)As is disposed below the cap layer and provides aresistive layer opening in registration with the cap layer opening andhaving a first width. A Schottky layer of Al_(y)In_(1−y)As is disposedbelow the resistive layer. An undoped channel layer is disposed belowthe Schottky layer. A semi-insulating substrate is disposed below thechannel layer. A top surface of the Schottky layer beneath the resistivelayer opening provides a recess having a second width smaller than thefirst width. A gate electrode is in contact with a bottom surface of therecess provided by the Schottky layer.

[0005] With such structure, uniform device characteristics such asbreakdown voltage, output currents, and pinch-off voltage areachievable, as is a high yield of acceptable devices.

[0006] In accordance with another feature of the invention, asemiconductor structure is provided having a Schottky layer adapted tobe etched at a first etch rate by an etchant. The semiconductorstructure also has a contact layer disposed above the Schottky layer andadapted to be etched by the etchant at a second etch rate that issubstantially faster than the first etch rate. The contact layerprovides an opening exposing a region of a top surface of the Schottkylayer, the region having a first width. The region of the top surface ofthe Schottky layer provides a recess of a second width smaller than thefirst width.

[0007] In a preferred embodiment of the invention, the Schottky layercontains aluminum, with an etch rate of about 0.1 Å/second relative to asuccinic acid etchant, while the contact layer is substantially free ofaluminum, having an etch rate of about 5 Å/second relative to succinicacid etchant. Such composition allows the transistor's contact layer tobe selectively etched with succinic acid to form the opening whileleaving the Schottky layer substantially intact. Thus, uniform devicecharacteristics such as breakdown voltage, output currents, andpinch-off voltage can be achieved and a high yield of acceptable devicesproduced.

[0008] In accordance with another feature of the invention, a transistorstructure is provided having a Schottky layer adapted to be etched at afirst etch rate by an etchant and a contact layer disposed above theSchottky layer and adapted to be etched by the etchant at a second etchrate that is substantially faster than the Schottky layer's first etchrate. In this structure, a region above a portion of a top surface ofthe Schottky layer is substantially free of the contact layer. Theportion of the top surface of the Schottky layer has a first width andprovides a recess having a second width smaller than the first width andadapted to receive a gate electrode.

[0009] In a preferred embodiment of the invention, the Schottky layercomprises at least about 35 percent Aluminum and the contact layercomprises less than about ten percent Aluminum.

[0010] In accordance with another feature of the invention, a method offorming a semiconductor is provided. The method includes forming aSchottky layer adapted to be etched by a first etchant at a first etchrate and forming a contact layer above the Schottky layer adapted to beetched by the first etchant at a second etch rate that is substantiallyfaster than the first etch rate. The first etchant is o applied to etchthe contact layer to expose a portion of the Schottky layer. A secondetchant is applied to etch the portion of the Schottky layer exposed bythe first etchant.

[0011] In a preferred embodiment of the invention, the Schottky layercontains Aluminum while the contact layer is substantially free ofAluminum. Further, the first etchant includes a carboxylic-acid basedwet etchant.

[0012] Embodiments of the invention may provide one or more of thefollowing advantages. The invention saves time and money inmanufacturing HEMTs. It also eliminates or decreases the need to etch adevice and periodically test the device for certain characteristics.Uniformity of device characteristics on a wafer can be improved.

[0013] Other advantages will be apparent from the following descriptionand from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross sectional diagrammatical sketch of a doublerecessed HEMT according to the invention; and

[0015] FIGS. 2-4 are cross sectional diagrammatical sketches of thedouble recessed HEMT of FIG. 1 in various stages of manufacture.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0016] Referring now to FIG. 1, a high electron mobility transistor(HEMT) 10 is shown. Here, transistor 10 has a source electrode 12 and adrain electrode 14. The electrodes 12 and 14 are in ohmic contact with acap layer 16. The cap layer 16 here is Ga_(0.47)In_(0.53)As, about 70 Åthick, and has a doping concentration of about 5×10¹⁸ cm⁻³. Disposedbelow the cap layer 16 is a recess or resistive layer 18. The resistivelayer 18 here is Ga_(0.47)In_(0.53)As, about 300 Å thick, and undoped.The cap and resistive layers 16 and 18 form a contact layer 50. Disposedbelow the resistive layer 18 is a Schottky layer 20, here undopedAl_(0.60)In_(0.40)As about 200 Å thick. The cap and resistive layers 16,18 provide an opening 38 from a surface 56 to a top surface 42 of theSchottky layer 20. The top surface 42 of the Schottky layer 20 providesa recess 44 with a bottom surface 48. In Schottky contact with theSchottky layer 20 at the bottom surface 48 is a gate electrode 22. Adoped pulse layer 24 is disposed below the Schottky layer 20. Here thepulse layer 24 is silicon and has a doping concentration of about 2×10¹²cm⁻². Disposed below the pulse layer 24 is a spacer layer 26. The spacerlayer 26 here is Al_(0.48)In_(0.52)As, about 30 Å thick, and undoped.Disposed below the spacer layer 26 is a channel layer 28. The channellayer 28 here is Ga_(0.47)In_(0.53)As, about 200 Å thick, and undoped. Asecond spacer layer 30 is disposed below the channel layer 28. Here thespacer layer 30 is Al_(0.48)In_(0.52)As, about 50 Å thick, and undoped.Disposed below the spacer layer 30 is a second pulse layer 32. Here thepulse layer 32 is silicon and has a doping concentration of 1×10² cm⁻²,providing a silicon pulse ratio of 2:1 between the first pulse layer 24and the second pulse layer 32 to help linearize the performance of thetransistor 10. Disposed below the pulse layer 32 is a buffer layer 34.The buffer layer 34 here is Al_(0.48)In_(0.52)As, about 2000 Å thick,and undoped. Disposed below the buffer layer 34 is a semi-insulating InPsubstrate 36.

[0017] The Schottky layer 20 can be undoped, as shown, or doped. Anundoped Schottky layer provides a higher breakdown voltage than with adoped Schottky layer 20. A doped Schottky layer 20 reduces resistancewhich lowers the breakdown voltage and increases conduction compared toan undoped Schottky layer 20.

[0018] As shown, transistor 10 has a double recess structure including afirst recess 39, formed by the opening 38 and the top surface 42 of theschottky layer 20, and the second recess 44. The first recess 39 isprovided by the cap layer 16 and the resistive layer 18. Side walls 40of the first recess 39 are provided by the cap and resistive layers 16,18 from the surface 56 to the top surface 42 of the Schottky layer 20.The first recess 39 exposes a first width W1 of the Schottky layer 20 ata top level 43 of the Schottky layer 20. The second recess 44 has asecond width W2 at the bottom surface 48, the width W2 being smallerthan the width W1. The second recess 44 is provided by the top surface42 of the Schottky layer 20 and has side walls 46 extending from the top43 of the Schottky layer 20 to the bottom surface 48.

[0019] The cap and resistive layers 16, 18 have different materialcomposition than the Schottky layer 20. The Schottky layer 20 includesGroup III-V material, here aluminum and indium. Sixty percent of theGroup III-V material in the Schottky layer 20 is aluminum and fortypercent is indium. To provide desirable device characteristics, there ispreferably at least 35 percent aluminum in the Schottky layer 20, andless than about ten percent aluminum in the cap and resistive layers 16,18. The cap and resistive layers 16, 18 are preferably substantiallyfree of Aluminum, though they can contain up to about ten percentAluminum and still provide desirable device characteristics.

[0020] The cap and resistive layers 16, 18 have a different etch ratethan the Schottky layer 20 to provide etch selectivity. The Schottkylayer 20 is adapted to be etched at a first etch rate by an etchant. TheAl_(0.60)In_(0.40)As Schottky layer 20 shown has an etch rate of about0.1 Å/second when exposed to an etchant of succinic acid, which is acarboxylic-acid based wet etchant. The cap and resistive layers 16, 18are adapted to be etched by the etchant at a second etch rate that issubstantially faster than the first etch rate. The Ga_(0.47)In_(0.53)Aslayers 16, 18 have etch rates of about 5 Å/second when etched bysuccinic acid.

[0021] A method of forming a semiconductor device such as transistor 10is now described, referring to FIGS. 1-4. FIG. 2 shows the forming oflayers 16, 18, and 20. FIGS. 3 and 4 show the etching of layers 16, 18,and 20. FIG. 1 shows the finished transistor 10.

[0022] The method of forming transistor 10 in FIG. 1 includes formingthe Schottky layer 20 and the cap and resistive layers 16, 18 above theSchottky layer 20. An etchant is applied to the cap and resistive layers16, 18 to etch them and expose the top surface 42 of the Schottky layer20. Another etchant is applied to etch the exposed top surface 42 of theSchottky layer 20 to produce the recess 44.

[0023] Referring to FIG. 2, forming the semiconductor layers 16, 18, and20 is now described. As shown in FIG. 2, the substrate 36 is providedand the buffer layer grown on the substrate 36 by molecular beam epitaxy(MBE). Over the buffer layer 34 the pulse layer 32 is grown by MBE anddoped by silicon. Over the pulse layer 32 the spacer layer 30, thechannel layer 28, and the spacer layer 26 grown by MBE. Over the spacerlayer 26 the pulse layer 24 is grown by MBE and doped by silicon. Overthe pulse layer 24 the Schottky layer 20 is grown by MBE. Referring nowto FIG. 3, the contact layer 50, including the cap layer 16 and theresistive layer 18, is formed by MBE on the Schottky layer 20 tocomplete the formation of an intermediate structure 54. A wet etchprocess for mesa isolation is performed by applying 1:8:160H₂SO₄:H₂O₂:H₂O for about 20 seconds to define the mesa. Then, 6:1succinic acid:H₂O₂ is applied for about 90 seconds to selectively etchback the InGaAs channel layer 28. This forms a channel notch (not shown)to help prevent shorting of the channel layer 28 to the gate electrode22 via a conductor (not shown) running up the side of the mesa.

[0024] Referring to FIGS. 3 and 4, etching the intermediate structure 54is now described. As shown in FIG. 3, a first etchant, here acarboxylic-acid based wet etchant, specifically 6:1 succinic acid:H₂O₂is applied to the top surface 56 of the cap layer 16. Electron beamlithography is used with the succinic acid and the succinic acid isapplied for enough time, e.g., about 60 seconds, to etch the contactlayer 50 at the second etch rate to form the opening 38. This exposesthe top surface 42 of the Schottky layer 20, selectively forms the firstrecess 39, and completes the formation of an intermediate structure 58.Because the first etch rate of the Schottky layer 20 is substantiallyslower than the second etch rate of the contact layer 50 in response tothe succinic acid, the succinic acid essentially does not etch theSchottky layer 20. The first etch is a selective etch.

[0025] Now referring to FIG. 4, intermediate structure 58 is etched. Asecond etchant, e.g., 1:1:100 H₃PO₄:H₂O₂:H₂O is applied to a portion ofthe top surface 42 of the Schottky layer 20 exposed by the succinic acidfor enough time to etch the Schottky layer 20, e.g., 10 seconds. Thisetching forms the second recess 44, and completes the formation ofintermediate structure 60.

[0026] Referring to FIG. 1, electrodes 12, 14, and 22 are added to theintermediate structure 60 to complete the transistor 10. The source anddrain electrodes 12 and 14 are in ohmic contact with the top surface 56of the cap layer 16. These ohmic contacts for the source and drainelectrodes 12 and 14 are fabricated using a 900 Å AuGe-2000 Å Aumetallurgy at 375° C. The gate electrode 22 is in Schottky contact withthe bottom surface 48 of the Schottky layer 20. The gate electrode isformed by depositing a resist layer, not shown, exposing the recess 44.Schottky metal of 500 Å Ti-500 Å Pt-4000 Å Au is deposited over theresist layer on the recess 44. The resist layer is lifted off to removeunwanted metal, leaving the gate electrode 22.

[0027] The transistor 10 shown in FIG. 1 has been fabricated and tested.The transistor 10 had a typical carrier sheet density of about 3×10¹²cm⁻², Hall mobility of 8300 cm²/V-sec at room temperature, maximumoutput current in the range 590-640 mA/mm, and breakdown voltage in therange 12.3-14.4 V.

[0028] Other embodiments are within the spirit and scope of the appendedclaims. For example, the contact layer 50 can be a single layer, dopedor undoped.

What is claimed is:
 1. A semiconductor structure comprising: a Schottkylayer adapted to be etched at a first etch rate by an etchant; and acontact layer disposed above the Schottky layer and adapted to be etchedby the etchant at a second etch rate that is substantially faster thanthe first etch rate; wherein the contact layer provides an openingthrough the contact layer exposing a region of a top surface of theSchottky layer, the region having a first width; and wherein the regionof the top surface of the Schottky layer provides a recess of a secondwidth smaller than the first width.
 2. The semiconductor recited inclaim 1 wherein the Schottky layer contains Aluminum.
 3. Thesemiconductor recited in claim 2 wherein the Schottky layer comprises atleast about 35 percent Aluminum.
 4. The semiconductor recited in claim 3wherein the Schottky layer is Al_(0.6)In_(0.4)As.
 5. The semiconductorrecited in claim 1 wherein the contact layer comprises less than aboutten percent Aluminum.
 6. The semiconductor recited in claim 1 whereinthe contact layer is substantially free of Aluminum.
 7. A transistorstructure comprising: a Schottky layer adapted to be etched at a firstetch rate by an etchant; and a contact layer disposed above the Schottkylayer and adapted to be etched by the etchant at a second etch rate thatis substantially faster than the first etch rate; wherein a region abovea portion of a top surface of the Schottky layer is substantially freeof the contact layer, the portion having a first width; wherein theportion of the top surface of the Schottky layer provides a recess of asecond width smaller than the first width; and wherein the recess of thesecond width is adapted to receive a gate electrode.
 8. The transistorrecited in claim 7 wherein the Schottky layer comprises at least about35 percent Aluminum and the contact layer comprises less than about tenpercent Aluminum.
 9. A method of forming a semiconductor comprising:forming a Schottky layer adapted to be etched by a first etchant at afirst etch rate; forming a contact layer above the Schottky layeradapted to be etched by the first etchant at a second etch rate;applying the first etchant to etch the contact layer to expose a portionof the Schottky layer; and applying a second etchant to etch the portionof the Schottky layer exposed by the first etchant; wherein second etchrate is substantially faster than the first etch rate when using thefirst etchant.
 10. The method recited in claim 9 wherein the Schottkylayer contains Aluminum.
 11. The method recited in claim 10 wherein theSchottky layer comprises about 35 percent Aluminum.
 12. The methodrecited in claim 11 wherein the contact layer is substantially free ofAluminum.
 13. The method recited in claim 11 wherein the first etchantincludes a carboxylic-acid based wet etchant.
 14. The method recited inclaim 13 wherein the first etchant is succinic acid.
 15. The methodrecited in claim 11 wherein the second etchant is applied for apredetermined time.
 16. A transistor structure comprising: a sourceelectrode; a drain electrode; a doped cap layer of Ga_(x)In_(1-x)Asdisposed below and in ohmic contact with the source electrode and thedrain electrode and providing a cap layer opening; an undoped resistivelayer of Ga_(x)In_(1-x)As disposed below the cap layer and providing aresistive layer opening in registration with the cap layer opening andhaving a first width; a Schottky layer of Al_(y)In_(1−y)As disposedbelow the resistive layer; an undoped channel layer disposed below theSchottky layer; and a semi-insulating substrate disposed below thechannel layer; wherein a top surface of the Schottky layer beneath theresistive layer opening provides a recess having a second width smallerthan the first width; and wherein a gate electrode is in contact with abottom surface of the recess provided by the Schottky layer.
 17. Thetransistor recited in claim 16 wherein the Schottky layer is doped.